Word Clock Generator

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Beavis

Member
Joined
Dec 31, 2006
Messages
5
Does anyone know about Word clock generators. I need one in my studio to sync some pieces of equipment.

I have been looking around on the net and prices for these units are from £70 to £900

Does anyone know how easy/difficult these are to make?

Cheers

Chris Beavis
 
if all you want to do is generate a steady 44.1KHz or 48KHz then that should be relatively easy to do with a crystal and a counter.

You could get 2 crystals, each 512xfS
So... 22.5792MHz and 24.576MHz with a switch between them, and run them into an 8bit counter, which essentially divides the clock by 512 to give 44.1kHz or 48kHz.

From there, you could run the signal into some clock drivers or standard buffers, and out.

If you want to recieve a clock signal then I suggest using some Schmmit trigger gates to tidy up the signal and buffers to re-transmit the signal.

Cheers
R
 
this might make an ideal clock buffer for you:

http://focus.ti.com/docs/prod/folders/print/cdc208.html

although i'm sure just some standard logic or an opamp would do the trick.

/R
 
Hi cheers for the reply.

All i need to do is generate a steady 44.1 or 48 into 4 BNC connectors.

I'm new to all this diy stuff so i'm lost

From there, you could run the signal into some clock drivers or standard buffers, and out.

clock drivers?

8bit counter?

I have no idea :oops:

Can you give me some pointers

Cheers for any help

Chris Beavis
 
Talking about Wordclock-generators (& sorry for hijacking this thread a bit): I'm confused a bit by the big differences in quoted jitter-data.

All kinds of data float around: some wordclock generators claim jitter less than 3 ps, while the AES/EBU standard for serial digital audio allows up to +/- 20 ns of jitter in the signal etc etc.

Obviously most sources must be talking about different kinds of jitter (many exist) and/or frequencies or different signals in a system and/or using vastly different conditions (& then fail to list those circumstances).


Regards,

Peter
 
Peter,

I'll give it a shot.

My understanding is that the AES/EBU standard allows up to +/- 20nS of jitter on the incoming stream.

The 3pS (or 50pS on some S/PDIF recievers) is a measure of the additonal jitter caused by the device.

Cheers

/R
 
[quote author="Rochey"]give me 24 hours :)[/quote]

Chris - I owe you some more information.

At this point, I think you need to do a little more reading on digital logic. It'll help you understand the basics of what you're going to do.

Crystals are some of hte most reliable clock sources. (and pretty much the most simple). However, most of them are in the MHz range (not the kHz range that you're wanting).

What a lot of people do in their design is use a high speed clock that is 256x the frequency they want, then divide the clock down.
A clock divider is the same as a counter. It's counts the incoming clock pulses, and after 256 (or whatever number you set) pulses, it's output will go high. After another 256, it's output will go low and so on.

Essentially, your circuit will look very simple:

High Speed Clock --> Clock Divider (counter) --> Buffered Outputs
 
[quote author="Rochey"]Peter,

I'll give it a shot.

My understanding is that the AES/EBU standard allows up to +/- 20nS of jitter on the incoming stream.

The 3pS (or 50pS on some S/PDIF recievers) is a measure of the additonal jitter caused by the device.

Cheers

/R[/quote]

Thanks Rochey for chiming in. Doesn't sound unlikely.

Unfortunately I realized there are yet a few more variables here; we have the actual datastream but also the wordclock signal (with for instance 1 or 256 times the sample frequency), so jitter specs also need to be accompanied by which frequency we're actually talking about, which in practice they hardly seem to do, making a comparison or understanding fuzzy.

I saw that 3 ps jitter spec being quoted for a 'cure-it-all' replacement clock (12.288MHz=256*fs) for say a CD-player. Sounds like it sure is good, but probably a few orders of magnitude better than would be noticable.

Bye,

Peter
 
[quote author="Beavis"]Does anyone know how easy/difficult these are to make?[/quote]
Fifteen minutes of soldering, if you don't care too much about jitter.

Ingredients:

- one 12.288MHz 5V crystal oscillator, for 48k word clock. Easiest to solder is DIP (such as Digi-Key part SE1733-ND) or metal can.
- one 74HCT4040, in a DIP package
- one 74HC245, in DIP.
- three 100nF ceramic capacitors.
- one 75 Ohm resistor.
- a small piece of perfboard (printed circuit board for experiments with holes on a 0.1in grid)
- a BNC connector, for the word clock cable. This should be a 75 Ohm impedance model (although a 50 Ohm model will likely work with minimal degradation)
- a 5V power source (in a pinch, 3 AA batteries will do).

Recipe:
- General: this is hi-frequency stuff. KEEP ALL WIRES AS SHORT AS POSSIBLE.
- Hint: Do a dry run on perfboard before soldering anything. See which placement allows for the shortest connections.
- Get the datasheet for your particular crystal oscillator. These invariably have four pins: one ground, one output, one VCC/+5V and one NC/OE. Ignore the last pin, you can leave it open.
- Connect all GND pins together. Close as you can!
- Connect all VCC pins together. Close as you can!
- Put a 100nF capacitor across the supply pins of each IC, with one capacitor leg to the GND pin and one capacitor leg to the VCC pin. Again, shortest wires are best. Optimal placement of the caps is likely on top of the ICs (for this step, the oscillator counts as an IC).
- Connect pin 11 of the 74HCT4040 (MR) to ground. This wire needn't be extra-ultra-short.
- Connect the output of your crystal oscillator to pin 10 of the 74HCT4040 (/CP).

Now, the 74HCT4040 is a chained divider which divides its input signal by powers of two. We need a 48KHz word clock, this equals 12.288MHz / 256. This divisor is available at output Q7, pin 13 of the 74HCT4040. Only the '4040 doesn't have enough oomph to drive a wordclock cable, this is where the 74HC245 comes in.

- Connect pins 2 thru 9 (A1..A8) of the 74HC245 together. Either use lots o'little jumpers ore one big blob of solder, just be careful not to overheat the part.
- Connect pins 11 thru 18 (B8..B1) of the 74HC245 together in the same way.
- Connect pin 1 (DIR) of the 74HC245 to VCC. Easiest way is to wire it to pin 20 of the 74HC245. This wire needn't be ultra short.
- Connect pin 19 (/OE) of the 74HC245 to ground.
- Connect pin 13 of the 74HCT4040 to pins 2..9 of the 74HC245
- Connect one end of the 75 Ohm resistor to pins 11..18 of the 74HC245
- Connect the other end of the 75 Ohm resistor to the center conductor of the BNC connector.
- Connect the shell of the BNC connector to ground.
- Carefully re-check all your connections
- Apply +5V power between ground and VCC

There you go, your very own 48k word clock generator! Parts cost (without supply and case) likely less than a fiver.

(Don't get some of the words/expressions ? Use Google. Still don't get 'em ? Ask here but post the best link you could find, it's usually easier for us to add to information that's already out there than to write it all up from scratch).

JDB.
 
[Much more on word clock, jitter and related subjects in Dan Lavry's PSW forum]
[quote author="clintrubber"]Unfortunately I realized there are yet a few more variables here; we have the actual datastream but also the wordclock signal (with for instance 1 or 256 times the sample frequency), so jitter specs also need to be accompanied by which frequency we're actually talking about, which in practice they hardly seem to do, making a comparison or understanding fuzzy.[/quote]
Jitter only really matters when it comes to converter clocks, or their sources (like word clock, in a primitive PLL like the ADA8000 seems to use). For the impact on audio, the phase noise (the frequency transform of the jitter) appears to make quite a difference on the 'sound'.

[quote author="clintrubber"]I saw that 3 ps jitter spec being quoted for a 'cure-it-all' replacement clock (12.288MHz=256*fs) for say a CD-player. Sounds like it sure is good, but probably a few orders of magnitude better than would be noticable.[/quote]
Would that one happen to be sold by a gent from your locale ?

A recent thread linked to a graph showing jitter-versus-dynamic range curves. I can't seem to find that one right now, but for the worst-case scenario the math isn't too hard. Here goes.

What jitter does is shifting the sampling instant. The result is that the larger a signal's slew rate, the larger the effect of jitter. As a result, higher frequencies will suffer more from jitter.

Take a sine wave. Its maximum slew rate occurs at zero-crossing, for:

dV/dt = 2*pi*f*A*cos(0) = 2*pi*f*A, where A is the amplitude.

For a 0dBFS (rms) sine, a maximum occurs at the top of the frequency band, say 20kHz:

dV/dt = 2*pi*20000*sqrt(2) = 178k/sec = 105dBFS for a 1-second RMS jitter.

This also shows that a 10x increase in jitter will increase its impact (raises the jitter-induced noise floor) by 20dB. So a first-order approximation is:

10ns jitter -> (105-20*log(10^8)) = -55dBFS
1ns jitter -> -75dBFS
100ps jitter -> -95dBFS
10ps jitter -> -115dBFS
3ps jitter -> -125dBFS

Keep in mind that these are worst-case jitter effects for 20kHz 0dBFS sine waves, decreasing by 6dB per octave that the frequency is lowered. This HF impact is named as the reason why jitter is often felt to 'decrease the airiness' and 'muddle up the high end'.

So yes, for a CD-player 3ps jitter could be considered overkill, but not by very much.

JDB.
[I might be off by an order of 2, since it's not quite clear to me if '3ps jitter' means +/- 3ps or not]
 
JD,

I assume that jitter noise level would be similar to the THD+N number on an ADC?

So, an ADC that usually has a -110dB THD+N would be fine until you hit a jitter level of 10ps or so?

Thats very interesting - the PLL inside the ADAT chip (AL1402G decoder) is specified as 1.5nS which would give an equivelent noise figure worse than -75dBFS...

have I got my dB's mixed up?
 
How would i build this system to allow 4 seperate outs running off the same clock?

I think i'll go buy some parts tomorrow.

Can you buy crystals like you can resistors?

Is there a specific one thats worth getting?

Cheers

Chris Beavis

Thanks for the replies, slowly getting my head around it.
 
I'd say it's still a little bit too soon (no offense).

best place to start seeing what parts are used are on EVM's from different manufacturers. For instance, Have a look at the PCM4202 EVM from TI.

We put 2 different crystals on there (one which is a multiple of 44.1KHz and teh other a multiple of 48kHz).

In your shoes, I would be tempted to try out the circuit in some digital modelling software like digital works. Google for it, there's a free version.

Any basic stuff like that, I always simulate it to make sure I haven't missed something obvious.
 
[quote author="jdbakker"][Much more on word clock, jitter and related subjects in Dan Lavry's PSW forum] [/quote]
Thanks for that link!

Jitter only really matters when it comes to converter clocks, or their sources (like word clock, in a primitive PLL like the ADA8000 seems to use). For the impact on audio, the phase noise (the frequency transform of the jitter) appears to make quite a difference on the 'sound'.
The relation between phase noise & jitter (translating figures into each other) seems a bit vague and/or requiring proper accompanyment(sp?) by the relevant conditions but which often lack.
Formula from section 3, page 4:
http://eesof.tm.agilent.com/pdf/jitter_phasenoise.pdf
(link down for some reason today)

[quote author="clintrubber"]I saw that 3 ps jitter spec being quoted for a 'cure-it-all' replacement clock (12.288MHz=256*fs) for say a CD-player. Sounds like it sure is good, but probably a few orders of magnitude better than would be noticable.
Would that one happen to be sold by a gent from your locale ?[/quote]
Most likely we're talking about the same person indeed:
http://www.tentlabs.com/Products/Components/XO/index.html

A recent thread linked to a graph showing jitter-versus-dynamic range curves. I can't seem to find that one right now, but for the worst-case scenario the math isn't too hard. Here goes.
Thanks for the clear maths. The +/-20ns as 'allowed' by the AES/EBU standard is the actually quite 'bad' (things may have become quite worse by then) but as you said it's a worst case calculation here. And FS-20kHz-signals in audio are rare to say the least.

This also shows that a 10x increase in jitter will increase its impact (raises the jitter-induced noise floor) by 20dB. So a first-order approximation is:

10ns jitter -> (105-20*log(10^8)) = -55dBFS
1ns jitter -> -75dBFS
100ps jitter -> -95dBFS
10ps jitter -> -115dBFS
3ps jitter -> -125dBFS

So yes, for a CD-player 3ps jitter could be considered overkill, but not by very much.
I can see that now, thanks. It's the 'best' figure I've seen so far. Surprised a bit that other 'masterclocks' seem to be worse by a few orders of magnitude.
For instance the RME Word Clock Module MKII states:
Low Jitter Design: typical 2.5 ns (PLL / Test), < 1 ns (Masterclock)
I'm not sure though I get fooled by the frequency this all is happening. The RME-figure is say at 44k1Hz and the Tent-spec at say 11.2896 MHz
(256*fs). I guess we need to correct the jitterspec [ps] for these different frequencies, right ? (Just like we need to do when comparing oscillator phase noise specs [dBc/Hz] at different frequencies).

[I might be off by an order of 2, since it's not quite clear to me if '3ps jitter' means +/- 3ps or not]
I understand, the info didn't state this.

Thanks,

Peter
 
[quote author="clintrubber"][quote author="jdbakker"]Jitter only really matters when it comes to converter clocks, or their sources (like word clock, in a primitive PLL like the ADA8000 seems to use). For the impact on audio, the phase noise (the frequency transform of the jitter) appears to make quite a difference on the 'sound'.[/quote]
The relation between phase noise & jitter (translating figures into each other) seems a bit vague and/or requiring proper accompanyment(sp?) by the relevant conditions but which often lack.
Formula from section 3, page 4:
http://eesof.tm.agilent.com/pdf/jitter_phasenoise.pdf
(link down for some reason today)[/quote]
Thanks for the link. They seem to use a rather theoretical and simplified model for most of the calculations; these folks have some real-world measurements (and I am inclined to believe them).

[quote author="clintrubber"]Thanks for the clear maths. The +/-20ns as 'allowed' by the AES/EBU standard is the actually quite 'bad' (things may have become quite worse by then) but as you said it's a worst case calculation here.[/quote]
They have a different purpose in mind: locking onto the signal at the receiver end. IIRC an AES link can have pulse times on the order of 100ns; 20ns would be 0.2UI, and that's a reasonable upper limit to jitter for a digital receiver to lock onto, even when the eye pattern is closing due to noise, reflections and group delay.

[quote author="clintrubber"]And FS-20kHz-signals in audio are rare to say the least.[/quote]
Sure, but keep in mind that jitter impacts fast slewing signals most, and music has plenty of those (hi-hats, anyone ?). Jitter will distort the same signals that are degraded by slow-slewing amplifiers, albeit in a different way. The 20k sine wave is just a convenient example for calculations, and nowhere near the worst signal that a converter can get to see.

[quote author="clintrubber"][quote author="jdbakker"]So yes, for a CD-player 3ps jitter could be considered overkill, but not by very much.[/quote]
I can see that now, thanks. It's the 'best' figure I've seen so far. Surprised a bit that other 'masterclocks' seem to be worse by a few orders of magnitude.
For instance the RME Word Clock Module MKII states:
Low Jitter Design: typical 2.5 ns (PLL / Test), < 1 ns (Masterclock)
I'm not sure though I get fooled by the frequency this all is happening. The RME-figure is say at 44k1Hz and the Tent-spec at say 11.2896 MHz
(256*fs). I guess we need to correct the jitterspec [ps] for these different frequencies, right ? (Just like we need to do when comparing oscillator phase noise specs [dBc/Hz] at different frequencies).[/quote]
Sort of, yes, but it's not that clear-cut. That 48k word clock with 1ns jitter will need to be passed to a PLL to generate an MCLK for the converters. The PLL's loop filter will improve the jitter some, on the other hand the PLL's noise may make matters worse, not to mention the reference spurs.

An important point here is that no PLL can improve a good low-noise crystal oscillator. Dan Lavry makes this point much more eloquently than I could, but the bottom line is that (a) an electrically-tuneable XO must have lower Q than a fixed-frequency one, and lower Q = more phase noise, and (b) pretty much any PLL will have more noise than the amplifier in the XO. So if you want best jitter performance, don't use that word clock input.

[quote author="Rochey"]I assume that jitter noise level would be similar to the THD+N number on an ADC?[/quote]
Mostly, yes.

[quote author="Rochey"]So, an ADC that usually has a -110dB THD+N would be fine until you hit a jitter level of 10ps or so?[/quote]
I would have to say no, since psycho-acoustics play a role too. Those -110dB THD+N are dominated by THD (all modern ADCs that I've seen have a THD level of 6..8dB over the noise floor). As far as I can tell, harmomic distortion sounds different than the non-harmonic distortion caused by jitter. Being a conservative designer, I try to keep the theoretical jitter noise below the converter noise floor.

Then again, some people appear to like the effects of jitter. There is a 14-page flamefest on Dan Lavry's forum on this subject which is well worth a read. On one side there's Dan Lavry and Bob Katz, who say that jitter will change your recordings in a non-reversible way, and that that's why you'd want as little jitter as possible. On the other side are some folks from (mostly) Apogee, claiming that some of their customers prefer the sound of external clocks like the Big Ben, even though they might increase jitter.

It's like back when I still shot a few dozen rolls of film every month. I'd gone through great pains to ensure that the process I used to develop my negatives was as consistent and benign as possible. Others would experiment with funky chemicals and (shudder) light sources during development.

Some people like tube sound, others like the sound of iron, both of which distort the sound in one way or the other. Maybe some people like the sound of jitter distortion for certain kinds of program material. I think I'm on Dan's side here. Especially for live recordings I'd rather not have any distortion mechanism present that I can't turn off.

[quote author="Rochey"]Thats very interesting - the PLL inside the ADAT chip (AL1402G decoder) is specified as 1.5nS which would give an equivelent noise figure worse than -75dBFS...

have I got my dB's mixed up?[/quote]
See above, no telling how much impact that 1.5ns jitter has on the converter clock. The fine folks at Wavefront might have included some more context, too, like the phase noise spectrum. Even so, 1.5ns jitter (or 1.26ns jitter on BCLK) isn't much to be proud of.

JDB.
 
it strikes me that designing your own pll must be near impossible if you have jitter on the incoming clock.

For DAC's, I think it's probably easier to get an Sample Rate Converter for your input, and just run the DAC with your own Crystal. A decent SRC (even a theoretical one) running at 144dB should keep any SRC noise out of the picture.

That's all fine if you're recieving data... but until the world decides to put SRC's on every input, we'll still have to syncrhonise to a system somewhere. *sigh*.

back to PLL design then...
 
[quote author="Rochey"]it strikes me that designing your own pll must be near impossible if you have jitter on the incoming clock.[/quote]
It's not too hard if you can assume the sending system has a sane (ie: crystal-derived) clock. Vari-Speed need not apply.

The best/cheapest way to DIY a PLL that I can see ATM is a dual acquisition/tracking loop. First have a microcontroller do a frequency measurement of the incoming wordclock up to, say, 1ppm relative to the VCXO. Now have a DAC shift your VCXO to this frequency. After that keep tracking phase shifts between your regenerated wordclock and incoming WC with a slow digital PLL driving a second DAC with a low-pass filter after it. If the PLL's bandwidth is <=1Hz then any reference spurs in the VCXO output will be too low to be audible.

However...

[quote author="Rochey"]For DAC's, I think it's probably easier to get an Sample Rate Converter for your input, and just run the DAC with your own Crystal. A decent SRC (even a theoretical one) running at 144dB should keep any SRC noise out of the picture.[/quote]

...and I'm inclined to believe that that's the best option for ADC's, too. The SRC4392 looks pretty good on paper, and I use it as my Plan A rate converter in the HDD recorder. Then again, the SRC4392 doesn't appear to do Word Clock locking so we'll need some sort of PLL for that anyway.

JDB.
 
You can find a complete word clock schematic at the following link. It is at the Symetrix site:

http://support.symetrixaudio.com/

Search for the GENx6 which is file #142

http://support.symetrixaudio.com/cgi-bin/symetrix.cfg/php/enduser/std_adp.php?p_faqid=83&p_created=1132273590&p_sid=kaCKGMri&p_accessibility=0&p_redirect=&p_lva=&p_sp=cF9zcmNoPSZwX3NvcnRfYnk9JnBfZ3JpZHNvcnQ9JnBfcm93X2NudD01MTEmcF9wcm9kcz0mcF9jYXRzPSZwX3B2PSZwX2N2PSZwX3NlYXJjaF90eXBlPWFuc3dlcnMuc2VhcmNoX25sJnBfcGFnZT04&p_li=&p_topview=1
 
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