As much as i can get away with - in a U67 (re)design i did within the last year, i spaced the B+ traces away from anything else by a good 2-3mm or so on every side. Call it "worst case scenario" thinking...
So here is actually the long answer to the like from four weeks before. Late, but there have been holidays, work and a little girl with the bad luck of being my little daughter which kept me from getting busy here again
.
Let’s dig into the topic a bit more than “whatever we get away with” ;-):
First of all – the compliance check gave that all noted problematic points from the comments above are in compliance with the IPC2221B standard table. Voltage driven copper traces to voltage driven copper (polymer coated) have to be 0.4 mm minimum, pad to pad (uncoated) 0.8 mm minimum and pad (uncoated) to polymer coated copper has to be 0.4 mm (see definitions under reference 2). All points of concern raised fulfill these criteria. The table presented in the article about the standard is actually quite old (see link to article about the creepage and clearance above and reference 1 below). The values are from 1998 and have not changed a lot since then – so I cannot comprehend the shock about these numbers. Some even consider them very conservative. So to sum up, this is not the “bare minimum”, but the generally minimum distance which is in line with one of the main industrial safety standards. Newer standards, even imply lower distances depending on the voltage. For example regarding the IEC 62368-1 (published 2021), the pad-trace distance in the C12 / ELAM251 board, which was mentioned here before with concerns, would require a minimum distance of 0.1 mm. This standard is complied to by times 4 and reflects a quite strict one (end consumer products; see below).
So just in brief, I checked through the most common projects here (old and new) and the IPC2221B standard is pretty much met by the handful I picked and had data from. So the IPC can be seen as a standard, this forum actually seems to agree on.
Nevertheless, the general 2-3 mm suggested is definitely not met by the majority of these projects. But surely you did your research yourself well, and know about that already.
Therefore, it may be advantageous to find better arguments than “… whatever I get away with …”. This forum has and is a highly technical one, with a ton of rich information. So let’s add to that with going actually into the matter.
As said, the IPC is an industrial standard. However, when checking the corresponding IEC standards it becomes obvious, that ALL standards rigorously differentiate polymer covered PCBs from eg. self-etched ones, or bare copper planes. There is an obvious reason for that: Polymer coating of traces is a way to avoid several of the issues or at least hampers them severly (eg. arcing, dendritic growth, pollution issues, humidity). This can be just seen from the fact that for bare traces your sea level height matters, for polymer coated there is no such limit given when you consult the IPC standard.
But what about other standards?
Most other references go to the IEC 60950-1 standard. You can find a detailed calculator under reference 3. Important to note, this standard differentiates as well as the IPC2221 polymer coated traces from others. However, the numbers are in the same ball park with eg. 0.6 mm for 250V.
Very important to note with the IEC 60950-1 is, that it is actually outdated and has been replaced by IEC 62368-1. As far as I know the numbers are very much the same but you will find much more information on the IEC 60950-1 on the net. Therefore I mentioned it here.
The IEC 62368-1 (see reference 4) is a standard for end consumer products (eg. Audio, video etc.; it covers external PSUs as well as outlined in the scope of the standard). It assumes a usage at about 2000 m sea level maximum. Numbers regarding spacing for printed circuit boards are given in chapter G.13 and referenced in Table G.13 of the standard for polymer coated traces. The numbers are much more staggered, and are for higher voltages in line with the IPC (eg. 283V is 0.4 mm), for “lower” voltages much lower (eg. 141V is 0.1 mm; NOTE: JUST FOR POLYMER COATED BOARDS; conditions are clearly stated within the standard).
However, the pad to pad creepage distances are severly higher than in the IPC. How come: The IEC standard actually mentions in its scope that it covers products also used in conditions, you barely find tube microphones in (eg. tropic conditions are mentioned by name). Humidity is here a much higher factor and a key driver for the increased distances compared to the IPC2221B standard.
So for this standard we finally find the pad to pad distances mentioned above, actually a bit higher. Minimum safe Pad-pad distance at 320V is 3.2 mm (see Table 17 of the standard, which gives the general creepage distances valid for non-covered traces too). However, this only refers to the open pads. Polymer coated Traces still run with 0.56 mm, even considering their distance to open pads (clearly stated within the standard; see chapter G.13).
So actually, you do not get away with 2-3 mm as stated above, if you want to hold the IEC 62368-1 standard, and this is also the most common point, where current GDIY projects show incompliance to the IEC standard.
__________________________________________________________________________________________
Summarizing the above, the PCBs have always and do also in future version comply with the IPC standard (industrial standard).
However, as asked, we would not dare to not go into full revision and ALL PCBs have been revised and do comply now additionally with the IEC 62368-1 standard regarding all voltages in the lethal range, as can be seen from the attachments.
All new files will be uploaded with the reference that these are no self-etching projects. For your preview, all layouts are attached as PDF here too. So you can check yourself.
However, one can make up his own mind – as the PCBs have always met one of the commonly accepted safety standards (IPC2221B) – if the comments made above bear the arguments to support the safety issues raised. All data and references can be found below from my side. All general design conditions are given in the text. If something remains unclear, do not hesitate to ask.
This should in no way diminish or play down the comments and issues raised above and if you have more I am happy to discuss. If you would have just asked you could get all information beforehand – so your judgement may be more precise instead of suspicious. Of course any standards you got to buy and read on your own.
But back to designs and technical information:
New design conditions have been adopted to meet the IEC 62368-1 for high voltages in addition to the already met IPC2221B. Maybe important: we did not go below the 0.4 mm trace spacing for all lines in cases where high voltages are present anywhere on the board, although this would be fully in agreement with the IEC but it may breach the IPC in some cases.
Regarding all PSUs the minimum spacing has been increased to 0.8 mm for traces. All PADs fulfill the IEC 62368-1 with regard to spacing (see Table 17 of the standard). The B+ supply has all the way significantly higher distances. The terminal blocks had to be upgraded to 5.08 mm spacing to become compliant with the IEC standard. 2.54 mm lead spacing cannot meet the safety regulations of the IEC standard regarding the run voltages. Still the initial lead spacing (2.54 mm) does comply with the IPC2221B standard.
All updated versions can be found in the threads itself – numbers are given here in addition and PDFs are attached to this reply:
PSUs:
C12/ElaM251 – V 2.3
U67 – V 2.2
MICs:
U47 – V 3.3 (not published yet)
C12 – V 3.7
ElaM251 – V 3.5
others:
TubeDI: T-DI – V 3.2 (not published yet)
PLEASE NOTE THAT NONE OF THESE VERSIONS IS ELIGIBLE FOR SELF ETCHING OR OPEN TRACES!!!
The U67 mic is in the making. Prototype is up and running, but the distances have to be adopted to the IEC standard, which is regarding the part count and the space the most challenging of the designs as we decided that the design should stay true to the original design.
Last but not least and coming back to the first paragraph – sorry for the late answer. In addition to the above made points, there was a bit of research necessary to find the references required. Additionally, the rework of the boards took a bit of time as well and I did not want to come back empty handed as I promised revisions.
Hope we have added just a little bit to the information found in this forum. Guess as the production of PCBs is increasing the matter of standards is maybe a highly valuable one. So maybe instead of asking for FORUM tribunals it may be a good suggestion to start a thread on that topic. I’m sure that others with more experience are happy to reference more standards and have maybe even better tools at hand.
So maybe this thing can start of something very positive as the question of design rules has not been raised here lately to my knowledge and there is tons of knowledge about safety standards and good practice here for sure. Feel free to add
.
I'm actually surprised the board fab was able to manufacture the boards, with trace / pad spacing THAT tight.
