> I also assume that the 66ohm reactances is why the B+ drops down to 179V rather than the 185V calculated for the 10K dropping resistors.
No. As mentioned, the caps are open-circuit at DC. They may show small changes in calculated DC voltage depending how the calculation or meter handles DC+ripple, but negligible. I came out at 179VDC instead of 185VDC because I estimated a good AC voltage to start from, and didn't bother to go around and refine my estimate. Anyhow, 179, 185 is all the same to tubes.
> Is that 66ohms related to ESR?
No. ESR will influence ripple reduction, but cap-makers mostly get ESR down low enough that it is not a big deal. 3300/66 is 34dB, the target for 100dB in 3 stages.
I think you need to go (C)-R-C-R-C, CF supply, -R-C-R-C, first stages. The CF supply can be a little dirtier than the inputs, but still has to be pretty clean.
> I can also lower the values of the dropping resistors
For best economy, you want big resistors. Ripple reduction per stage is proportional to R*C. Big C costs money, big R has no direct cost. Of course it has the indirect cost of either delivering less voltage or requiring more transformer voltage (at the same current, hence higher VA rating) to keep final DC the same. In the ideal world, you would compare the cost of iron against the cost of caps and find a minimum-cost zone, In today's world you take the transformer voltage you can buy (or already have), figure how much R you can tolerate, and then figure caps.
If you are not going into production, no reason to go cheap, 200V 100uFd-500Ω-100uFd-500Ω-100uFd, CF, -3.3K-100uFd-3.3K-100uFd works. That's a little overkill, but going to 47uFd each is not quite good enough (8mV ripple at the CF plate). A very-minimum-capacitance design would use different size caps in each section, but the 10-for price on caps is so much better than the one-each price that making them all the same is rational. Peak voltage on the first cap is 280V; 400V for all is conservative, 300V will probably last years easily. Either a 10-pack of 47uFd 300V (five 94uFd) or a 10-pack of 100uFd with five leftover for another project.
> The calculation for multiple stages assumes
Yeah, if we'd gone for a few dB in each stage the rough rules become too rough to use. And if we go for many-many dB per stage, we have to watch ESR and stray wiring resistance. PSD started with ESD of 2Ω, which means a 500Ω R-C stage can't get over ~46dB/stage. 2Ω is actually about right for a hi-volt 100uFd, but the real limit is the ~16Ω capacitive reactance at 120Hz. DCR drops as uFd rises. DCR in a good cap should not be a limit unless the power frequency is 400Hz or above (it is the limit in KHz switchers).
Man, put a 5-stage filter in PSD, output keeps rising for over a minute. And running the sim eats a LOT of virtual memory: 760Megs in a 510Meg-RAM machine, thrash-a-matic.
No. As mentioned, the caps are open-circuit at DC. They may show small changes in calculated DC voltage depending how the calculation or meter handles DC+ripple, but negligible. I came out at 179VDC instead of 185VDC because I estimated a good AC voltage to start from, and didn't bother to go around and refine my estimate. Anyhow, 179, 185 is all the same to tubes.
> Is that 66ohms related to ESR?
No. ESR will influence ripple reduction, but cap-makers mostly get ESR down low enough that it is not a big deal. 3300/66 is 34dB, the target for 100dB in 3 stages.
I think you need to go (C)-R-C-R-C, CF supply, -R-C-R-C, first stages. The CF supply can be a little dirtier than the inputs, but still has to be pretty clean.
> I can also lower the values of the dropping resistors
For best economy, you want big resistors. Ripple reduction per stage is proportional to R*C. Big C costs money, big R has no direct cost. Of course it has the indirect cost of either delivering less voltage or requiring more transformer voltage (at the same current, hence higher VA rating) to keep final DC the same. In the ideal world, you would compare the cost of iron against the cost of caps and find a minimum-cost zone, In today's world you take the transformer voltage you can buy (or already have), figure how much R you can tolerate, and then figure caps.
If you are not going into production, no reason to go cheap, 200V 100uFd-500Ω-100uFd-500Ω-100uFd, CF, -3.3K-100uFd-3.3K-100uFd works. That's a little overkill, but going to 47uFd each is not quite good enough (8mV ripple at the CF plate). A very-minimum-capacitance design would use different size caps in each section, but the 10-for price on caps is so much better than the one-each price that making them all the same is rational. Peak voltage on the first cap is 280V; 400V for all is conservative, 300V will probably last years easily. Either a 10-pack of 47uFd 300V (five 94uFd) or a 10-pack of 100uFd with five leftover for another project.
> The calculation for multiple stages assumes
Yeah, if we'd gone for a few dB in each stage the rough rules become too rough to use. And if we go for many-many dB per stage, we have to watch ESR and stray wiring resistance. PSD started with ESD of 2Ω, which means a 500Ω R-C stage can't get over ~46dB/stage. 2Ω is actually about right for a hi-volt 100uFd, but the real limit is the ~16Ω capacitive reactance at 120Hz. DCR drops as uFd rises. DCR in a good cap should not be a limit unless the power frequency is 400Hz or above (it is the limit in KHz switchers).
Man, put a 5-stage filter in PSD, output keeps rising for over a minute. And running the sim eats a LOT of virtual memory: 760Megs in a 510Meg-RAM machine, thrash-a-matic.
