Charge amplifier for piezoelectric sensors

[capnrefsmmat]

So I have a weird project. I'd like to build a hydrophone using a piezoelectric cylinder, like in this Instructable. Piezoelectric sensors have high output impedance, so you need a high-impedance buffer or preamp to use them; the Instructable has a simple phantom-powered one based on a dual op-amp.

But I wanted to try something different, for no other reason than it's interesting. I happen to own some test-and-measurement accelerometers that use ICP/IEPE powering, which is a way of powering the sensor preamp with two wires (i.e. coax), rather than requiring an XLR cable. The recorder provides a constant-current supply (4 mA at up to 30V). With no signal, the signal wire is at about 12 V, and the voltage varies with the signal. The current source maintains 4 mA throughout. I have background and a schematic in an old blog post. I've already built the power supply and used it with other sensors, so I could reuse it for this.

According to a book I have (Piezoelectric Accelerometers with Integral Electronics), the standard approach is to use a charge amplifier with a FET input stage and BJT output stage for low output impedance. It gives this "schematic":


Not the world's most detailed schematic. But you can see the outline: FET, BJT, R2 and R3 bias the FET, R1 sets a low-pass filter if you need it. The feedback capacitor Cf sets the charge gain. The book gives formulas for the lower and upper -3dB frequency limits based on the piezo capacitance, the resistor values, and Cf.

The question is how to fill in the detail of this schematic. I have basically 0 experience here, and I couldn't find any information on charge amps running from constant current sources (vs, say, using an op-amp on a normal power supply).

With some LTspice tinkering, I arrived at the following:



As you can see, I'm planning on a JFE150, and I've added in biasing for the BJT's base. In simulation, this appears to work -- except the frequency range does not match the book's formulas at all. (With these values, the low-pass rolloff should be at over 200 kHz, but it simulates at around 17 kHz.) I'm pretty sure I'm biasing the BJT base wrong, and maybe that's the problem, but I'm all out of ideas.

I guess my main question is: does this FET/BJT configuration make sense, and if so, how should the biasing work on each?

After that, I need to figure out how to set R2 and R3. Their ratio is important for biasing, but their absolute value isn't, so I'm not sure if I want to aim high or low. But that's a little easier to figure out after the circuit works properly.

 

[abbey road d enfer]

As you can see, I'm planning on a JFE150, and I've added in biasing for the BJT's base. In simulation, this appears to work -- except the frequency range does not match the book's formulas at all. (With these values, the low-pass rolloff should be at over 200 kHz, but it simulates at around 17 kHz.) I'm pretty sure I'm biasing the BJT base wrong, and maybe that's the problem, but I'm all out of ideas.

Can you post your LTspice file (the .asc)?

I guess my main question is: does this FET/BJT configuration make sense,

I believe it does, somewhat.

and if so, how should the biasing work on each?

Let's see with teh help of LTspice.

After that, I need to figure out how to set R2 and R3. Their ratio is important for biasing, but their absolute value isn't,

I think their absolute value directly relates to sensitivity of the whole arrangement. In first approximation, gain is R4/R3.

 

[capnrefsmmat]

Sure, here's the LTspice file and the JFE150 model. (Not sure if LTspice includes that in the .asc or if you need it separately.)

For what it's worth, the book claims the following things, which I guess hint at the configuration the author envisioned:

Voltage gain is Cpe/Cf

-3 dB lower corner frequency is 1 / (2 pi Rin Cf), where Rin = Rb (R2 + R3) / R3.

- 3dB upper corner frequency is 1 / (2 pi R1 Cpe).

By my math, this should be flat out to over 200 kHz, but it's not, so evidently I'm not matching what the author envisioned.

edit: My current theory is that there shouldn't be a direct path from the piezo to the BJT's base. The whole point of using a JFET is to provide a high input impedance; having the BJT in parallel with that defeats the purpose, and maybe that's rolling off the high end. Not sure what to do with the BJT base instead, though.

 

[molke]

If you haven’t already seen it, there’s also a fairly detailed description of a 4 mA current loop microphone system on the ESP site, though for an electret and no charge amp as far as I can tell, so not sure whether this helps in any way.

 

[abbey road d enfer]

Sure, here's the LTspice file and the JFE150 model. (Not sure if LTspice includes that in the .asc or if you need it separately.)

You haven't joined the symbol for the FET. The standard LTspice symbol does not work.

 

[abbey road d enfer]

By my math, this should be flat out to over 200 kHz, but it's not, so evidently I'm not matching what the author envisioned.

What you're seing at the output is the image with gain (or rather attenuation) of the input voltage.
Look at the input voltage; it's not flat, no way it could be flat since it consists in a current source in parallels with a capacitor.
I couldn't make your circuit doing what you expect.
One of the problems is that the feedbak capacitor loads the collector of the BJT, so the OLG rolls off significantly at HF.
You would need to reduce the output impedance of the output stage.
I have made a quick and dirty variant here, that works a little better, but is far from perfect.

The original sketch shows at least two FET's and two BJT's. I believe they are necessary.

 

[capnrefsmmat]

If you haven’t already seen it, there’s also a fairly detailed description of a 4 mA current loop microphone system on the ESP site, though for an electret and no charge amp as far as I can tell, so not sure whether this helps in any way.

Yeah, I was looking at that. I actually ended up emailing him about something else in that article, and discussed accelerometers briefly. Apparently he has a dead one but was not able to reverse engineer it (all tiny unmarked surface-mount components), so he's not sure how to build the charge amp either.

I also happen to have a dead accelerometer, and it's from the 80s so maybe it has simpler components, but I'm a little afraid to start boring through the steel case.

What you're seing at the output is the image with gain (or rather attenuation) of the input voltage.
Look at the input voltage; it's not flat, no way it could be flat since it consists in a current source in parallels with a capacitor.
I couldn't make your circuit doing what you expect.
One of the problems is that the feedbak capacitor loads the collector of the BJT, so the OLG rolls off significantly at HF.
You would need to reduce the output impedance of the output stage.
I have made a quick and dirty variant here, that works a little better, but is far from perfect.
View attachment 114969

Interesting, thanks. I think part of the issue is I'm not sure how best to model the piezo, I think I want to be looking at the output voltage vs. the input charge, but I'm not sure how to work with charge.

The original sketch shows at least two FET's and two BJT's. I believe they are necessary.

I think the sketch is showing that it can be either a JFET or a MOSFET, and either a PNP or an NPN transistor; but only one of each is needed. That matches the text. Here's more of the description:

The input stage having high input impedance to match the PE transducer’s high impedance is based on a n-channel JFET or a n-channel MOSFET. The output stage providing low output impedance is based on either a PNP or a NPN bipolar transistor. Other options may include additional stages between these two stages.

In Fig. 3.1 [the diagram I posted], ePE and CPE represent the open-circuit PE transducer’s output voltage and its electrical capacitance, respectively. ePE is directly proportional to the PE transducer’s charge sensitivity QPE and inversely proportional to CPE [see expression (1.21)]. Cf is the feedback capacitance, Rb is biasing resistor (typically it has a high value, e.g., 10^9 Ω), resistors R2 and R3 create the resistive divider. The biasing resistor Rb together with resistive divider R2/R3 forms the negative dc feedback circuit which provides the amplifier’s stable operation over the specified temperature range (typically from -55 C to 125 C), bias for FET, and corresponding output bias voltage Vb. Vb depends on the FET parameters IDSS and VGS(off), which usually vary from device to device for the same type of FET. Therefore, resistors R2 and R3 are made variable to adjust Vb within some limits for different FET devices. This makes possible to use in the circuit all variations of FETs without the necessity of their selection, that would be a costly alternative.

I saw a paper by the same author suggesting using two BJTs in a Darlington pair when extra-low output impedance is needed.

 

[ccaudle]

I'm not sure how best to model the piezo

I have usually seen them modeled as a voltage source in series with a capacitor, but I suppose a current source in parallel is just the Thevenin equivalent, so I don't see why that would not work as well.

The original schematic doesn't make much sense though. I think you would have to AC couple to get the DC levels correct. What low frequency limit do you need?
There may be a way to get a DC coupled circuit to work using something like Schoeps microphone buffer approach, a PNP output device emitter directly to the output pin, but you will likely still need a cap somewhere to couple the JFET into the bipolar.

 

[abbey road d enfer]

This version seems to simulate reasonably well.

 

[capnrefsmmat]

Very nice, that seems to work. I guess the key was to AC couple the JFET to the BJT? I'll have to play with this so I can understand it better.

Will any PNP do here, or should I be looking for something specific?

 

[abbey road d enfer]

Very nice, that seems to work. I guess the key was to AC couple the JFET to the BJT? I'll have to play with this so I can understand it better.

Still I think there's room for improvement.
This version extends fequency response.

But there's still a lot of work to do to optimize it.
There's a better way to bias the BJT.

Will any PNP do here, or should I be looking for something specific?

There are not much specific constraints there, just that the max voltage should be adequate and the higher the Hfe the better.