[quote author="bcarso"]There's a somewhat misleading drafting detail in that schematic: one might think, with the capacitor symbols and particularly with the "+" notations, that C3 and C4 were 'lytics and rather large in value. I see that ADI is inconsistent with their schematics. Sometimes the caps are shown with two straight plates, sometimes with the one plate curved, and in the above, one curved and with the plus sign.[/quote]
The Dec '82 IEEE-article doesn't show C3,4 with the '+', but happens to have a plus-sign for all caps in the detailed schematic.
Moreover, if the polarity of an electrolytic cap would have been of significance here (which it isn't of course), then the simplified & detailed schematics would have been different w.r.t. C3,4-polarity.
The values are not given anywhere I've looked, but I would rest assured that they are relatively small.
FWIW, the Feb '82 ISSCC digest has a pic of the chip but no overwhelming cap-areas. A total of 75pF of MOS-capacitance is reported.
C3,4 value can be estimated from the input transconductance and the 25MHz GBW-product.
BTW, in general, I think that the words 'new', 'novel' and 'technique' are often a bit overused in articles. Some authors look a bit too eager to plant a flag and don't notice that isle they just landed on is already inhabited... :wink:
Regards,
Peter